The 5-mask TFT process is a common a-Si TFT-LCD Array manufacturing flow that patterns the Gate electrode, active semiconductor stack, Source/Drain metal, passivation/via layer, and pixel ITO electrode through five lithography cycles.
Key Takeaways
- The 5-mask process is best understood as five repeated patterning cycles.
- Each mask forms one layer group that supports the final TFT switching function.
- IPS or other designs may add a common-electrode mask, so mask count is process-dependent.
Why the Process Starts From the Layer Stack
The Array process is organized around the TFT-LCD array substrate structure. In a TN-mode a-Si 5-mask example, the main layers are Gate electrode, Gate insulator, active layer, Source/Drain electrode, passivation, and pixel electrode.
Mask 1: Gate Electrode and Scan Line
Mask 1 forms the Gate electrode and scan line. The sequence is glass cleaning, PVD metal deposition, photoresist coating, exposure, development, wet etching, and photoresist stripping.
Mask 2: Gate Insulator, Semiconductor, and Ohmic Contact
Mask 2 forms the Gate insulator, a-Si semiconductor, and N+ a-Si ohmic contact. The sequence uses CVD deposition, photoresist coating, exposure, development, dry etching, and stripping.
Mask 3: Source/Drain, Data Line, and Channel
Mask 3 forms the Source/Drain electrodes, data line, and TFT channel. The sequence uses PVD metal deposition, lithography, wet etching, N+ etching, and photoresist stripping.
Mask 4: Passivation and Via
Mask 4 forms the passivation layer and via opening. The passivation protects the TFT channel, while the via creates the electrical path to the pixel electrode.
Mask 5: Pixel ITO Electrode
Mask 5 forms the transparent pixel ITO electrode. After ITO deposition, lithography, wet etching, and stripping, the 5-mask TFT Array substrate is complete.
5-Mask vs 6-Mask Context
IPS a-Si products can add a common electrode, so the process may require an additional mask compared with a 5-mask TN example. Mask count is therefore process-dependent, not a universal rule.
Frequently Asked Questions
What is the 5-mask TFT process?
It is an a-Si TFT-LCD Array flow that patterns five functional layer groups: Gate, active semiconductor, Source/Drain, passivation/via, and pixel ITO.
Why can IPS require six masks?
IPS structures include a common electrode, so they may add one mask compared with a simpler 5-mask TN structure.
Is 5-mask always the standard?
No. Mainstream a-Si TFT-LCD mask counts often fall around 5 to 7, depending on viewing mode, reliability target, and factory process design.
Technical References
The following industry references support the material properties, TFT backplane terminology, and process context used in this guide.
- Applied Materials: Amorphous Silicon
a-Si has long been a dominant active-matrix TFT-LCD semiconductor; its low mobility explains why oxide and LTPS are used for higher-performance backplanes. - AGC: Glass Substrates for TFTs (AN100)
TFT-LCD glass must be alkali-free, heat resistant, chemically stable, and dimensionally stable during array fabrication. - Nippon Electric Glass: Alkali-Free Glass Substrate OA-11
Alkali-free display glass uses very low alkaline oxide content and supports dimensional stability through TFT process temperatures. - SID / Wiley: Beyond Amorphous-Silicon TFTs
a-Si mobility is limited compared with newer high-mobility TFT materials, which helps explain material trade-offs in LCD backplane design.
Related Deep-Dive Guides
- Main TFT-LCD Array process guide
- TFT-LCD Array substrate structure
- TFT-LCD Array photolithography
- TFT-LCD Array materials
- Copper vs aluminum Gate electrodes
Related SuccessLCD Resources
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