TFT Display Pixel Clock & Interface Bandwidth Calculator
Enter the active resolution, refresh rate, colour depth and blanking of a TFT panel. The calculator returns the pixel clock, frame-buffer size and the bandwidth each display interface needs: parallel RGB, LVDS, MIPI DSI and SPI. Everything runs in your browser; nothing is sent until you choose to contact us.
1. Panel timing
The example timings are typical values for common panel sizes. Use the timing table in your own panel specification for design work.
2. Interface options
3. Results
| Total pixels per line × total lines | – |
|---|---|
| Pixel clock | – |
| Frame buffer (single / double) | – |
| Parallel RGB | – |
| LVDS single link (7:1) | – |
| LVDS dual link | – |
| MIPI DSI per-lane bit rate | – |
| SPI: frame rate at this clock | – |
| SPI: clock needed for the refresh rate | – |
MIPI D-PHY reference limits per lane: 1.5 Gbps (v1.1), 2.5 Gbps (v1.2), 4.5 Gbps (v2.0). LVDS transmitters and timing controllers each have their own maximum pixel clock; check the datasheets of the parts you use. SPI figures exclude command overhead and assume 16 bits per pixel for RGB565 and 24 bits on the wire for 18 and 24 bpp.
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How the calculator works
The pixel clock is the number of pixel periods per frame, including blanking, multiplied by the refresh rate: pixel clock = (H active + HFP + HBP + HSYNC) × (V active + VFP + VBP + VSYNC) × refresh rate. A 1024×600 panel with 1344 total pixels per line and 635 total lines at 60 Hz needs 1344 × 635 × 60 ≈ 51.2 MHz.
The frame buffer is width × height × bytes per pixel. RGB565 uses 2 bytes per pixel; RGB666 and RGB888 are usually stored as 3 bytes. A 480×272 RGB565 frame needs about 255 KB, which decides whether a microcontroller can hold it in internal RAM or needs external SDRAM or PSRAM. For partial draw buffers and SPI panels, use the MCU display RAM calculator.
Parallel RGB sends one pixel per clock on 16, 18 or 24 data lines plus clock, sync and data-enable signals. Single-link LVDS also sends one pixel per clock but serialises 7 bits per clock on each data pair: 3 pairs for 18 bpp and 4 pairs for 24 bpp, plus one clock pair. Dual-link LVDS sends odd and even pixels on two links, so each link runs at half the pixel clock.
MIPI DSI spreads pixel clock × bits per pixel across 1, 2 or 4 data lanes. Video-mode packets and blanking add overhead, so plan the lane rate with a margin above the raw figure. SPI displays are refreshed by the host one frame at a time, so the achievable frame rate is the SPI clock divided by the bits in one frame.
Frequently asked questions
What pixel clock does a 7-inch 800×480 TFT need?
With typical timing of 1056 total pixels per line and 525 total lines at 60 Hz, the pixel clock is about 33.3 MHz. The exact value depends on the porch and sync values in the panel specification.
When should I use LVDS instead of parallel RGB?
LVDS uses fewer wires and tolerates longer cables and electrical noise better than a 24-bit parallel bus, so it is common from about 7 to 15.6 inches and in industrial and automotive equipment. Parallel RGB suits shorter connections to MCUs and SoCs with a built-in RGB controller.
How fast can an SPI display refresh?
A 240×320 panel in RGB565 has 1,228,800 bits per frame, so a 40 MHz SPI clock gives at most about 32 frames per second before command overhead. Larger displays usually move to parallel RGB, MIPI DSI or a controller with its own frame memory.